Case Studies
ECG Artifact Recognition for Portable Defibrillation
Key Results
- 10 ms Automated Decision Latency
- 96.2% Rhythm Recognition Accuracy
- IEC 60601-2-4 and ERC 2021 Verified
About the project
A European medical device manufacturer developing its first dual-mode portable defibrillator engaged PerformaCode to design and implement an ECG artifact recognition and rhythm classification algorithm for automated shock decision support. The device targeted emergency and first-responder use cases and was required to operate reliably on low-power embedded hardware using a single-lead ECG signal.
The goal was to deliver fast, deterministic rhythm analysis under real-world conditions, including motion artifacts, electrode noise, and unstable signal quality, while supporting both adult and pediatric patient profiles within a single algorithm. PerformaCode was responsible for algorithm design, modeling, embedded implementation, and verification, delivering a production-ready component validated on clinical reference datasets and aligned with current defibrillation and ECG performance standards.
12
months
4
engineers
FP
delivery model
Client challenges
The client’s initial implementation relied on ready-to-use third-party ECG analysis algorithms that offered limited transparency, weak traceability, and insufficient control over clinical behavior. As the device evolved into a dual-mode portable defibrillator, this dependency became a risk. The existing algorithms did not provide deterministic behavior under artifact-heavy conditions, could not be cleanly adapted for pediatric patients, and offered no clear path to standards-traceable verification.
At the same time, the project was operating under aggressive timelines, with little tolerance for rework during verification and certification. Internal teams were focused on hardware design, system integration, and preparation of the overall compliance package, leaving limited capacity to prototype, validate, and harden a safety-critical ECG algorithm from scratch. The client needed a compliance-ready solution early, implemented without OS or platform dependencies, and delivered by engineers who understood both ECG signal processing and the practical expectations of medical device verification.
Tasks performed
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Analyzed and formalized requirements for ECG artifact recognition, shock decision logic, execution timing, and embedded constraints.
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Prototyped ECG signal processing algorithms for QRS detection, rhythm analysis, and artifact identification using MATLAB.
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Validated prototype behavior against reference ECG databases to assess detection accuracy and stability.
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Implemented ECG analysis algorithms in C++ without dependencies on a specific operating system, hardware platform, or external libraries.
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Developed artifact classification logic for shockable rhythms including ventricular fibrillation, ventricular tachycardia, and ventricular flutter.
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Implemented contraindication detection for non-shockable rhythms including supraventricular tachycardia, atrial fibrillation, atrial flutter, idioventricular rhythms, and asystole.
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Added pediatric mode support by adapting thresholds and rhythm parameters for pediatric ECG reference datasets.
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Optimized algorithm execution for deterministic timing and low resource usage on embedded targets.
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Designed and implemented the decision interface for signaling shock recommendation and contraindications to the defibrillator control software.
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Developed defibrillator control logic to identify sustained arrhythmias and manage the automatic defibrillation decision chain.
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Integrated ECG analysis with defibrillator control workflows using an agreed communication protocol.
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Validated algorithm behavior using simulation models and acceptance testing on the customer side.
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Prepared test reports and technical documentation to support verification activities and downstream certification.
Project results
10 ms Execution Time
ECG analysis and rhythm classification executed within a bounded 10 ms window during continuous monitoring, using deterministic signal-processing paths without OS-level dependencies.
96.2% Rhythm Accuracy
Shockable and non-shockable rhythm detection reached 96.2% accuracy on reference ECG datasets through iterative prototyping, parameter tuning, and validation against annotated signals.
Platform-Independent Algorithm
The algorithm was implemented in C++ without dependencies on a specific operating system, hardware platform, or external libraries, simplifying integration into the defibrillator software stack.
Dual Adult and Pediatric Modes
Adult and pediatric ECG analysis were delivered within a single algorithm through parameterized thresholds and mode-specific tuning instead of separate code paths.
Standards-Traceable Verification
Algorithm behavior was validated on reference ECG datasets aligned with IEC 60601-2-4 and current defibrillation guideline requirements, supporting downstream certification activities.
Value we bring
Compliance Built Into the Architecture
We design algorithms and system components so that verification, traceability, and standards alignment are inherent to the implementation. Deterministic behavior, clear interfaces, and testable decision logic allow products to move into verification without structural rework. This reduces late-stage compliance risk and keeps certification timelines predictable.
Fast Iterations With Production-Grade Outputs
We move in short, focused iterations but deliver results that are ready for real use. Prototypes are backed by test data, documentation, and traceability artifacts that can be reused in later development and verification phases. This enables rapid progress without accumulating technical or regulatory debt.
From Research Logic to Deterministic Systems
We turn research-grade models and prototype logic into deterministic, bounded implementations suitable for safety-critical devices. This is possible because the work is done by senior engineers with strong STEM backgrounds and hands-on experience across signal processing, embedded systems, and regulated development. Mathematical models are translated into explicit decision logic with defined timing and resource limits, ensuring behavior remains predictable when deployed on constrained hardware.
Technologies
- C/C++
- MATLAB
- ARM Cortex-M
- STM32
- Bare-Metal Embedded Systems
