Case Studies
Pre-Silicon Virtual Platform Engineering
Key Results
- 100+ device models delivered
- 1K+ virtual platform configurations
- 6–9 months shift-left enabled
About the project
A worldwide silicon vendor engaged PerformaCode to develop and maintain device and platform models for an industrial-strength full-system simulation environment used in pre-silicon software development and architecture exploration.
The simulation environment supported large-scale virtual platforms, including complex multi-processor configurations and clustered systems representative of telecom, networking, and data-center class deployments. Our team developed transaction-level device models and event-driven components operating under a deterministic scheduler that preserved serial semantics while allowing parallel execution on multicore hosts.
The scope included modeling CPUs, chipsets, and peripheral devices, and enabling complete software stacks including firmware, BSPs, BIOS, operating systems, kernel drivers, and user-level applications before physical hardware prototypes were available. The simulation core supported scalable execution, virtualization acceleration on compatible hosts, and just-in-time compilation for cross-architecture targets, enabling realistic software workloads to run in a virtual environment.
The platform was integrated into a broader engineering toolchain including debuggers, external simulators, and hardware emulation systems, allowing use in architecture exploration, complex debugging, and automated validation environments.
PerformaCode also provided full Level 2 and Level 3 engineering support for internal stakeholders and external users, resolving software and platform issues without access to physical hardware. The engagement has continued across multiple platform generations, with team size scaling between 11 and 55 engineers depending on program phase, maintaining a senior technical profile throughout.
20+
engineers
Ongoing
project duration
Agile T&M
delivery model
Client challenges
The virtual platform expanded from a development tool into a high-dependency engineering environment used across multiple silicon programs. Model coverage grew rapidly, requiring continuous implementation, validation, and maintenance of CPUs, chipsets, and peripheral devices across evolving platform generations.
Each silicon revision introduced specification changes that cascaded into updates of transaction-level models, interconnect behavior, firmware interfaces, and regression suites. Maintaining determinism and backward compatibility across configurations while scaling model count increased integration complexity.
The platform supported heterogeneous software stacks including firmware, BSPs, BIOS, multiple operating systems, kernel drivers, and user-space workloads. Model inaccuracies or scheduling inconsistencies directly impacted downstream software validation.
As adoption increased, the volume of Level 2 and Level 3 issues rose accordingly. Debugging had to be performed without hardware reference, often across firmware and kernel boundaries, under constraints of deterministic replay and repeatable execution.
Sustaining model accuracy, performance scalability, and high-severity issue resolution simultaneously required senior system-level engineering capacity.
Tasks performed
- Developed numerous virtual device models including audio controllers, network adapters, USB controllers, security modules, Super I/O components, CAN controllers, and communication controllers
- Modeled next-generation silicon platforms pre-release, enabling early firmware and OS development ahead of physical hardware availability
- Enabled Windows and Linux bring-up on virtual platforms, including complex driver and kernel-layer debugging
- Implemented device passthrough and host-device interaction mechanisms allowing guest operating systems to utilize host resources
- Developed deterministic reverse execution workflows to support deep root-cause analysis across firmware and kernel boundaries
- Built modular virtual platforms from configurable components including CPU, memory, interconnect, and peripheral subsystems
- Optimized model performance and scalability for multicore host execution environments
- Integrated virtual platforms with debugging, performance, and validation toolchains
- Provided full Level 2 and Level 3 support resolving escalations from internal and external users without hardware access
- Maintained and evolved models across multiple silicon generations, adapting to architectural changes and specification updates
- Supported large-scale multi-board and multi-processor configurations used for architecture and performance exploration
Project results
1,000+ configurations
More than 1,000 platform variants were supported by assembling systems from reusable CPU, memory, interconnect, and peripheral building blocks.
6–12 mo shift-left
Software stacks were brought up before hardware availability by enabling firmware, BSPs, BIOS, OS, and driver execution on virtual platforms.
30–50% faster integration
HW/SW integration cycles were shortened by validating boot flows, drivers, and workloads on virtual systems in parallel with silicon development, reducing late-stage churn.
40–70% faster debug
Root-cause turnaround improved using deterministic replay and reverse execution techniques, allowing engineers to step back from failures across firmware and kernel paths.
100+ device models
Over 100 virtual device models were implemented and maintained by delivering transaction-level models across multiple peripheral classes and platform generations.
100K+ regression runs
Pre-silicon stability was enforced through 100K+ automated regression executions across configurations and stacks, catching integration and model issues before hardware access.
Zero-hardware L2/L3 resolution coverage
Level 2 and Level 3 escalations were handled without physical prototypes by reproducing issues inside the virtual environment and debugging across firmware, BSP, driver, and OS layers.
Value we bring
Engineering for Pre-Silicon Reality
We design and validate software stacks in environments where hardware does not yet exist. This requires precise modeling of platform behavior, disciplined interface management, and continuous alignment with evolving silicon specifications. The practice reduces late-stage integration risk and allows firmware, BSP, and OS development to proceed in parallel with hardware programs.
Owning Level 2 and Level 3 Without Hardware
We take ownership of high-severity escalations and cross-layer defects without requiring physical prototypes. By debugging across firmware, BSP, kernel, and user-space boundaries inside deterministic virtual environments, we reduce response time and shield core silicon teams from operational overload. This improves end-user experience and supports broader platform adoption.
Scaling Senior Teams Without Losing Depth
We scale engineering capacity up and down according to program phase while maintaining a consistently senior technical profile. This requires rigorous hiring standards, strong architectural governance, and knowledge continuity across platform generations. The result is elasticity without loss of technical quality or decision-making maturity.
Technologies
- C/C++
- DML
- Python
- GCC
- Linux
- Windows
- Eclipse
- SVN
- Proprietary Simulation Scripting
“High code quality, highly detailed, documented and fast. You have worked with great independence and worked seamlessly with our domain owners.”
- Leading semiconductor platform developer
- Programmable Solutions Group Leader
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